RouteRTL SDK

RouteRTL is a unified, multi-vendor FPGA SDK engineered for high-efficiency hardware development. It provides a single CLI (rr) that drives project generation, simulation, synthesis, and verification across Xilinx, Intel/Altera, Lattice, and Microchip toolchains.

Owner: Daniel J. Mazure — License: MIT

🚀 Key Features

• Multi-Vendor Support: Seamlessly switch between Xilinx Vivado, Lattice Radiant, Altera Quartus, and Microchip Libero workflows.
• Unified CLI: 42+ commands via rr (or routertl) — rr init, rr sim, rr synth, rr lint, rr docker, rr doctor, and more.
• Automated Project Generation: Create reproducible projects from a single project.yml source of truth with rr init --template sensor_hub.
• Advanced Register Bank System:
  • Define registers in human-readable YAML.
  • Automatically generate VHDL packages, Python constants, and C headers.
  • Built-in versioning and consistency checks.
• Smart Dependency Management:
  • Automatic handling of external IP and VHDL libraries.
  • Auto-discovery of VHDL library assignments from source files.
• Modern Simulation Environment:
  • Cocotb integration for Python-based testbenches.
  • Combined VHDL/Verilog/SystemVerilog Support: Test mixed-language designs seamlessly.
  • Multiple Backends: NVC (recommended), GHDL, Verilator, and Icarus Verilog.
• Containerized Workflow: Docker environments for all major vendor suites and a lightweight open-source sim container.

Architecture

📂 SDK Structure

routertl/
├── sdk/
│   ├── cli/commands/      # CLI command implementations (rr <command>)
│   ├── cli/checks/        # rr doctor health checks
│   ├── engine/            # Core engine: project.yml parsing, build env
│   ├── engine/sim/        # Simulator backends (NVC, GHDL, Verilator, Icarus)
│   └── engine/init/       # rr init project scaffolding
├── routertl_core/         # Compiled core (Cython on release builds)
├── src/units/             # Reusable VHDL/SV utility entities
├── tools/docker/          # Docker environment scripts
├── docs/                  # User documentation
└── pyproject.toml         # Package definition

🛠️ Prerequisites

• Essential: Python 3.10+
• Simulation (pick one):
  • NVC (recommended, fastest for VHDL)
  • GHDL (alternative VHDL simulator)
  • Verilator v5.0+ (Verilog/SystemVerilog)
• Synthesis (as needed):
  • Xilinx Vivado
  • Intel Quartus Prime
  • Lattice Radiant
  • Microchip Libero SoC
• Optional: Docker (for containerized builds)

🚦 Getting Started

1. Install

pip install routertl

2. Initialize a Project

rr init --template sensor_hub --name my_project -y

This scaffolds project.yml, Makefile, directory structure, and git hooks.

3. Verify Your Environment

rr doctor

4. Simulate

rr sim                    # Interactive test selection
rr sim --all              # Run all tests
rr sim test_my_module     # Run a specific test

5. Lint & Synthesize

rr lint                   # Smart hierarchical linting
rr synth                  # Synthesize with configured vendor

🐳 Docker Environments

Pre-configured, reproducible build containers for all major EDA tools.

rr docker install sim      # Install base simulation image
rr docker shell sim        # Interactive shell
rr docker run sim "rr sim --all"   # Run command in container
rr docker status           # Dashboard: volumes, images, health

📚 Documentation

• User Guide — Comprehensive reference
• First Steps Tutorial — 20-minute walkthrough
• Cocotb Quickstart — Simulation guide
• Installation Guide — Detailed install instructions

📜 License

MIT License (Open Shell). PolyForm Shield (Core).