Language Support Roadmap
Multi-language support plan for the RouteRTL SDK. The SDK launched with VHDL-first support; SystemVerilog and mixed-language capabilities are being added incrementally.
Planned — v3.1
| # | Priority | Feature | Status | Affected Files |
|---|---|---|---|---|
| 1 | 🔴 High | SV regbank package generator | Planned | generate_regbank_pkg.py — add SV templates for types, masks, init vectors |
| 2 | 🔴 High | SV ROM-info package generator | Planned | gen_info_pkg.py — add --language flag and SV parameter output |
Planned — v3.2
| # | Priority | Feature | Status | Affected Files |
|---|---|---|---|---|
| 3 | 🟡 Medium | Mixed-language projects | Partial | Needs dual pre-compilation pipeline and per-file language tagging in project.yml |
| 4 | 🟡 Medium | Linter SV backend | Planned | smart_linter.py / linting.sh — add Verilator or Slang as SV lint backend |
Backlog
| # | Priority | Feature | Status | Affected Files |
|---|---|---|---|---|
| 5 | 🟢 Low | SV testbench stub generator | Backlog | cocotb-testgen — add SV module stub generation |
| 6 | 🟢 Low | Language auto-detection | Backlog | Infer hardware.language from file extension majority in sources.syn |
Completed
| Feature | Commit | Date |
|---|---|---|
hardware.language field in project.yml | — | 2026-02-09 |
SV-aware system_config_pkg stub in init_project.py | — | 2026-02-09 |
Dynamic SYS_CONFIG_RTL extension in Common.mk | — | 2026-02-09 |
| Language-aware pre-commit linter (skip Phase 1 for non-VHDL) | 06a8b1d | 2026-02-09 |