SPI Drivers

Native SPI Master and Slave bus functional models for cocotb testbenches. Pure-Python implementation supporting all 4 SPI modes (CPOL/CPHA combinations) with configurable word width, clock frequency, and chip-select polarity.

Quick Start

import cocotb
from routertl.sim import Tb
from routertl.sim.cocotb.tb.drivers.spi_master import SpiBus, SpiConfig, SpiMaster

@cocotb.test()
async def test_spi_sensor(dut):
    tb = Tb(dut)
    await tb.start_clock()
    await tb.reset()

    # Connect to SPI signals (auto-detects SCLK, MOSI, MISO, CS)
    bus = SpiBus.from_entity(dut, prefix="SPI_")

    # Configure: 8-bit words, 1 MHz, Mode 0 (CPOL=0, CPHA=0)
    config = SpiConfig(word_width=8, sclk_freq=1_000_000, cpol=False, cpha=False)

    master = SpiMaster(bus, config)

    # Full-duplex write (returns data read from MISO)
    rx_data = await master.write([0x9F, 0x00, 0x00])  # Read JEDEC ID
    tb.log.info(f"JEDEC ID: {[hex(b) for b in rx_data]}")

    # Read-only (sends zeros, returns MISO data)
    status = await master.read(1)

SPI Modes

Classes

::: sim.cocotb.tb.drivers.spi_master.SpiBus options: show_root_heading: true members: - from_entity - from_prefix

::: sim.cocotb.tb.drivers.spi_master.SpiConfig options: show_root_heading: true

::: sim.cocotb.tb.drivers.spi_master.SpiMaster options: show_root_heading: true show_source: true members: - init - write - write_nowait - read

::: sim.cocotb.tb.drivers.spi_master.SpiSlave options: show_root_heading: true show_source: true members: - init - load_response - get_received - clear_received - start - stop